Summer 2023Q5(B)
Discuss DMA.
Chapter 5
DMA and Buffering
Study DMA transfer sequence and buffering types used to bridge producer-consumer speed mismatch.
Estimated time: 21 min
DMA moves data directly between device and memory; buffers absorb speed differences.
This topic links architecture-level transfer flow with practical throughput improvement.
DMA Sequence
From notesClear explanation
CPU programs DMA registers, DMA requests bus transfer, device sends data to memory, DMA interrupts CPU after completion.
What it really means
CPU is dispatcher; DMA is moving truck.
Key takeaway
CPU overhead shifts from byte-wise copy to setup + completion handling.
Buffering Choices
From notesClear explanation
Single buffer is simple, double buffer overlaps producer and consumer, circular buffer supports continuous stream workloads.
What it really means
More buffers increase elasticity against speed mismatch.
Key takeaway
Buffering policy should match data arrival/consumption pattern.
DMA + Buffering Combined Flow
Added clarityClear explanation
CPU sets DMA descriptor and buffer addresses, device writes into active buffer, interrupt notifies completion, and consumer switches to filled buffer while DMA starts filling next buffer.
What it really means
Two hands working: one hand fills next bucket while the other empties previous bucket.
Example
Audio streaming uses circular buffers to avoid glitches while continuous DMA writes keep arriving.
Key takeaway
In exam answers, link DMA transfer and buffering policy together, not separately.
- - Thinking DMA eliminates CPU role entirely
- - Ignoring buffer type selection by workload
- - Not relating buffering to underflow/overflow behavior
- - DMA controller handles block transfers; CPU sets it up
- - Single, double, and circular buffering target different rates
- - Buffering improves throughput and smoothness
Effective overlap in double buffering improves utilization by parallelizing input and processing
Exam lens for this topic
What evaluators usually expect in structured exam answers.
Must-use keywords
- - dma
- - direct memory access
- - buffering
- - block oriented
- - stream oriented
Answer flow
- - Write exact definition in first line
- - Explain mechanism in ordered bullets
- - Add one short example or scenario
- - Close with key takeaway and one exam keyword
Practice Questions
Write short note on Direct Memory Access.
Source: Winter 2023 Q5(B)
Answer focus: Definition + detailed steps + advantage.
Write short note on DMA.
Source: IMP Questions
Answer focus: Compare with non-DMA read/write path.
Practice from papers (end-of-topic set)
These paper questions map directly to this topic. Solve now, then compare your structure with linked topics.
Winter 2023Q5(B)
Write short note on Direct Memory Access.
Question Bank Linked Here
Open all questionsSummer 2023Q5(B)
Discuss DMA.
Winter 2023Q5(B)
Write short note on Direct Memory Access.
How to answer linked exam questions
Full question bankSummer 2023 Q5(B)
Discuss DMA.
Answer pattern: concept -> intuition -> steps -> concluding point with one application.
Winter 2023 Q5(B)
Write short note on Direct Memory Access.
Answer pattern: concept -> intuition -> steps -> concluding point with one application.