Chapter 4

Paging, Demand Paging, and TLB

Master page/frame mapping, page fault handling, and translation acceleration via TLB.

Estimated time: 31 min

Program memory is split into pages; only needed pages are loaded into RAM frames.

This is core OS memory management and appears in both conceptual and numerical questions.

Core Paging Flow

From notes

Clear explanation

Virtual address is split into page number and offset; page table gives frame number; frame+offset forms physical address.

What it really means

Page number finds shelf, offset finds exact position on shelf.

Key takeaway

Paging removes need for contiguous process allocation.

Demand Paging + TLB

From notes

Clear explanation

Demand paging loads only required pages; TLB caches common translations so mapping stays fast.

What it really means

TLB is a pocket lookup card for frequently used page table entries.

Key takeaway

Performance depends on both page-fault rate and translation speed.

Page Fault Handling Steps

Added clarity

Clear explanation

On invalid page-table entry, CPU raises page-fault trap; OS validates access, loads page from disk into free frame (or replaces one), updates page table/TLB, and restarts faulted instruction.

What it really means

Missing book page is fetched from storage, indexed, then reading resumes from the same sentence.

Example

If free frames are unavailable, replacement policy chooses victim page before loading demanded page.

Key takeaway

Memorize page-fault sequence as ordered steps for diagram questions.

  • - Forgetting page size must equal frame size
  • - Mixing page number with offset bits
  • - Ignoring TLB hit vs miss cost
  • - Page table maps virtual page -> physical frame
  • - Page fault triggers disk fetch and table update
  • - TLB caches recent translations to avoid extra memory access
Physical Address = Frame Number x Page Size + Offset
Effective Access Time (conceptual) = (TLB hit ratio x hit path time) + ((1 - hit ratio) x miss path time)

Exam lens for this topic

What evaluators usually expect in structured exam answers.

Must-use keywords

  • - Page
  • - Frame
  • - Page Table
  • - TLB
  • - Page Fault

Answer flow

  • - Show virtual address split: page number and offset
  • - Explain page-table lookup and TLB hit/miss path
  • - Describe page-fault trap and recovery steps
  • - Add one numeric mapping example

Diagram expectations

  • - Paging with page table block diagram
  • - TLB lookup flow

Repeated pattern: Paging with diagram is one of the most repeated 4-7 mark questions.

Mini quiz

Quick self-check from this topic before moving ahead.

1. A page fault occurs when:

Practice Questions

  • Explain paging with diagram.

    Source: Summer 2023 Q4(B)

    Answer focus: Page/frame concept + MMU mapping path.

  • Discuss paging with example.

    Source: Winter 2023 Q4(A)

    Answer focus: Example-driven mapping and page fault behavior.

Practice from papers (end-of-topic set)

These paper questions map directly to this topic. Solve now, then compare your structure with linked topics.

Question Bank Linked Here

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How to answer linked exam questions

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Extra clarity files

These are clearly marked additions, separate from source notes.